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general description the max15050/max15051 high-efficiency switching reg- ulators deliver up to 4a load current at output voltages from 0.6v to (0.9 x v in ). the devices operate from 2.9v to 5.5v, making them ideal for on-board point-of-load and postregulation applications. total output-voltage accuracy is within 1% over load, line, and temperature. the max15050/max15051 feature 1mhz fixed-frequen- cy pwm operation. the max15050 features pulse-skip mode to improve light-load efficiency. the max15050 soft-starts in a monotonic mode and then operates in the forced pwm mode or pulse-skip mode depending on the output load current condition. the max15051 soft-starts in the monotonic mode and operates in the forced pwm mode. the high operating frequency allows for small-size external components. the low-resistance on-chip nmos switches ensure high efficiency at heavy loads while minimizing critical parasitic inductances, making the layout a much simpler task with respect to discrete solutions. following a simple layout and footprint ensures first-pass success in new designs. the max15050/max15051 incorporate a high-bandwidth (> 26mhz) voltage-error amplifier. the voltage-mode control architecture and the voltage-error amplifier permit a type iii compensation scheme to achieve maximum loop band- width, up to 200khz. high loop bandwidth provides fast transient response, resulting in less required output capaci- tance and allowing for all-ceramic capacitor designs. the max15050/max15051 feature an output overload hiccup protection and peak current limit on both high- side and low-side mosfets. these features provide for ultra-safe operation in the cases of short-circuit condi- tions, severe overloads, or in converters with bulk elec- trolytic capacitors. the max15050/max15051 feature an adjustable output volt- age. the output voltage is adjustable by using two external resistors at the feedback or by applying an external reference voltage to the refin/ss input. the max15050/max15051 offer programmable soft-start time using one capacitor to reduce input inrush current. a built-in thermal shutdown pro- tection assures safe operation under all conditions. the max15050/max15051 are available in a 2mm x 2mm, 16-bump (4 x 4 array), 0.5mm pitch wlp package. applications features internal 18m ? r ds(on) mosfets pulse-skip mode for high-efficiency light load (max15050) continuous 4a output current 1% output-voltage accuracy over load, line, and temperature operates from 2.9v to 5.5v supply adjustable output from 0.6v to (0.9 x v in ) adjustable soft-start reduces inrush supply current factory-trimmed 1mhz switching frequency compatible with ceramic, polymer, and electrolytic output capacitors safe startup into prebias output enable input/power-good output fully protected against overcurrent and overtemperature overload hiccup protection sink/source current for ddr applications 2mm x 2mm, 16-bump (4 x 4 array), 0.5mm pitch wlp package max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package ________________________________________________________________ maxim integrated products 1 ordering information 19-4915; rev 2; 3/10 evaluation kit available part temp range pin- package skip mode m a x1 5 0 5 0 e we + - 40c to + 85c 16 wlp yes m a x1 5 0 5 1 e we + - 40c to + 85c 16 wlp no + denotes a lead(pb)-free/rohs-compliant package. pin configuration appears at end of data sheet. output input 2.9v to 5.5v bst lx in en v dd gnd fb v dd comp pwrgd refin/ss gnd max15050 max15051 typical operating circuit server power supplies point-of-load asic/cpu/dsp core and i/o voltages ddr power supplies base-station power supplies telecom and networking power supplies raid control power supplies portable applications for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com.
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = v en = 5v, c vdd = 2.2f, t a = -40c to +85c, typical values are at t a = +25c, unless otherwise noted.) (note 4) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. in, pwrgd to gnd..................................................-0.3v to +6v v dd to gnd ..................-0.3v to the lower of +4v or (v in + 0.3v) comp, fb, refin/ss to gnd ....................-0.3v to (v dd + 0.3v) en to gnd................................................................-0.3v to +6v bst to lx..................................................................-0.3v to +6v bst to gnd ............................................................-0.3v to +12v lx to gnd ....................-0.3v to the lower of +6v or (v in + 0.3v) lx to gnd (note 1) ..-1v to the lower of +6v or (v in + 1v) for 50ns i lx(rms) ....................................................................................6a v dd output short-circuit duration .............................continuous converter output short-circuit duration ....................continuous continuous power dissipation (t a = +70c) 16-bump (4 x 4 array), 0.5mm pitch wlp (derate 20.4mw/c above +70c) ..............................1000mw thermal resistance (note 2) ja .................................................................................49c/w jc ...................................................................................9c/w operating temperature range ...........................-40c to +85c junction temperature ......................................................+150c operating junction temperature at maximum current (note 3)........................................+105c storage temperature range .............................-65c to +150c soldering temperature (soldering, 10s) ..........................+260c note 1: lx has internal clamp diodes to gnd and in. applications that forward bias these diodes should take care not to exceed the ics power dissipation limit of the device. note 2: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . note 3: operating the junction temperature above +105c will degrade the life of the device. parameter conditions min typ max units in voltage range 2.9 5.5 v v in = 3.3v 4.8 8 in supply current no load, no switching v in = 5v 5.3 8.5 ma total shutdown current from in v in = v bst - v lx = 5v, v en = 0v 10 20 a v dd rising 2.6 2.8 v dd undervoltage lockout threshold lx starts/stops switching, no load v dd falling 2.35 2.55 v v dd undervoltage deglitching 10 s v dd output voltage i vdd = 0 to 10ma 3.1 3.3 3.5 v v dd dropout v in = 2.9v, i vdd = 10ma 0.09 v v dd current limit v dd = 0v 20 37 ma bst max15050, v bst = 5v, v lx = 0v, no switching 10 bst supply current max15051, v in = v lx = 3.3v, v bst = 6.6v, no switching 250 a in to bst on-resistance v in = 3.3v, i in = 0.16a 4 pwm comparator pwm comparator propagation delay 10mv overdrive 20 ns pwm peak-to-peak ramp amplitude 1 v pwm valley amplitude 0.76 v
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = v en = 5v, c vdd = 2.2f, t a = -40c to +85c, typical values are at t a = +25c, unless otherwise noted.) (note 4) parameter conditions min typ max units comp comp clamp voltage high v dd = 2.9v to 5v, v fb = 0.5v, v refin/ss = 0.6v 2 v comp clamp voltage low v dd = 2.9v to 5v, v fb = 0.7v, v refin/ss = 0.6v 0.68 v comp slew rate v fb = 0.7v to 0.5v, v refin/ss = 0.6v 1.4 v/s comp shutdown resistance from comp to gnd, v in = 3.3v, v comp = 100mv, v en = v refin/ss = 0v 6 error amplifier fb regulation accuracy using external resistors 0.594 0.6 0.606 v open-loop voltage gain 115 db error-amplifier unity-gain bandwidth 26 mhz error-amplifier common-mode input range v dd = 2.9v to 3.5v 0 v dd - 2 v v fb = 0.7v, sink 1 error-amplifier maximum output current v comp = 1v, no switching, v refin/ss = 0.6v v fb = 0.5v, source -1 ma fb input bias current v fb = 0.7v 70 na refin/ss refin/ss common-mode range v dd = 2.9v to 3.5v 0 v dd - 2 v refin/ss charging current v refin/ss = 0.45v 6 8 10 a refin/ss offset voltage v refin/ss = 0.9v, fb shorted to comp -4.5 +4.5 mv refin/ss pulldown resistance v in = v dd = 3.3v, v refin/ss = 0.1v 300 lx (all bumps combined) lx on-resistance, high side i lx = -500ma v in = v bst - v lx = 3.3v 24 54 m lx on-resistance, low side i lx = 500ma v in = 3.3v 18 50 m high-side sourcing 5.4 8 low-side sourcing 7 low-side sinking 7 zero-crossing current threshold 0.2 skip high-side sourcing 0.58 a lx current-limit thresholds v in = 3.3v sink current-limit dac steps 4 steps v lx = 0v -10 lx leakage current v en = 0v v lx = 5v 10 a lx switching frequency v in = 3.3v 0.9 1 1.1 mhz lx maximum duty cycle v in = 3.3v 90 96 % lx minimum on-time v in = 3.3v 80 ns rms lx output current 4 a enable en input logic-low threshold (falling) 0.7 v
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package 4 _______________________________________________________________________________________ parameter conditions min typ max units en input logic-high threshold (rising) 1.5 v en input current v en = 0 or 5v 0.01 1 a thermal shutdown thermal-shutdown threshold +165 c thermal-shutdown hysteresis 20 c power-good (pwrgd) v fb falling, v refin/ss = 0.6v 87 90 93 power-good threshold voltage v fb rising, v refin/ss = 0.6v 92.5 % of v refin/ss power-good edge deglitch v fb falling or rising 48 clock cycles pwrgd output-voltage low i pwrgd = 4ma 0.03 0.15 v pwrgd leakage current v pwrgd = 5v, v fb = 0.9v, v refin/ss = 0.6v 0.1 1 a overcurrent limit (hiccup mode) current-limit startup blanking 112 clock cycles autoretry restart time 896 clock cycles fb hiccup threshold v fb falling 70 % of v refin/ss hiccup threshold blanking time v fb falling 36 s note 4: specifications are 100% production tested at t a = +25c. limits over the operating temperature range are guaranteed by design and characterization. electrical characteristics (continued) (v in = v en = 5v, c vdd = 2.2f, t a = -40c to +85c, typical values are at t a = +25c, unless otherwise noted.) (note 4) typical operating characteristics (v in = 5v, output voltage = 1.8v, i load = 4a, and t a = +25c, circuit of figure 1, unless otherwise noted.) efficiency vs. load current (v in = 5v) (max15050) m ax15050 toc01 load current (a) efficiency (%) 1 0.1 50 60 70 80 90 100 40 0.01 10 v out = 1.2v v out = 3.3v v out = 1.8v v out = 2.5v 40 60 50 80 70 90 100 0.1 1 10 efficiency vs. load current v in = 5v (max15051) max15050 toc01b load current (a) efficiency (%) v out = 3.3v v out = 2.5v v out = 1.8v v out = 1.2v efficiency vs. load current (v in = 3.3v) (max15050) m ax15050 toc02 load current (a) efficiency (%) 1 0.1 50 60 70 80 90 100 40 0.01 10 v out = 1.8v v out = 1.2v v out = 2.5v
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package _______________________________________________________________________________________ 5 typical operating characteristics (continued) (v in = 5v, output voltage = 1.8v, i load = 4a, and t a = +25c, circuit of figure 1, unless otherwise noted.) frequency vs. input voltage input voltage (v) frequency (mhz) 5.3 5.1 3.1 3.3 3.5 3.9 4.1 4.3 4.5 4.7 3.7 4.9 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 0.80 2.9 5.5 m ax15050 toc03 t a = +25 n c t a = -40 n c t a = +85 n c 40 60 50 80 70 90 100 0.1 1 10 efficiency vs. load current v in = 3.3v (max15051) max15050 toc02b load current (a) efficiency (%) v out = 2.5v v out = 1.8v v out = 1.2v line regulation (i load = 4a) max15050 toc04 input voltage (v) % output from normal 5.3 5.1 4.7 4.9 3.5 3.7 3.9 4.1 4.3 4.5 3.1 3.3 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 2.9 5.5 load regulation max15050 toc05 load current (a) % output from normal 3.0 3.5 2.5 2.0 1.5 1.0 0.5 04.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 load-transient response max15050 toc06 v out ac-coupled 200mv/div i out 2a/div 4a 1a 40s/div load-transient response max15050 toc07 v out ac-coupled 100mv/div i out 2a/div 2a 4a 40s/div switching waveforms max15050 toc08 v out ac-coupled 50mv/div i lx 1a/div v lx 2v/div 0v 400ns/div shutdown waveform max15050 toc09 v en 5v/div v out 1v/div 10s/div
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v in = 5v, output voltage = 1.8v, i load = 4a, and t a = +25c, circuit of figure 1, unless otherwise noted.) soft-start waveform max15050 toc10 v en 5v/div v out 1v/div 400s/div input shutdown current vs. input voltage max15050 toc11 input voltage (v) input shutdown current (a) 80 65 -25 -10 5 35 20 50 2 4 6 8 10 12 0 -40 v in = 3.3v v in = 5v max15050 toc12 i out 5a/div v out 1v/div hiccup current limit i in 2a/div 400s/div rms input current during short circuit vs. input voltage input voltage (v) rms input current (a) 5.3 5.1 4.7 4.9 3.5 3.7 3.9 4.1 4.3 4.5 3.1 3.3 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 2.9 5.5 m ax15050 toc13 v out = 0v feedback voltage vs. temperature max15050 toc14 temperature (c) feedback voltage (v) 60 35 10 -15 0.596 0.598 0.600 0.602 0.604 0.606 0.594 -40 85 soft-start with refin/ss max15050 toc15 i in 1a/div v refin/ss 500mv/div v out 1v/div v pwrgd 2v/div 400s/div starting into prebiased output with 2a load max15050 toc16 v en 2v/div v out 1v/div 0v 0v 0a 0v i out 2a/div v pwrgd 5v/div 400s/div starting into prebiased output with no load max15050 toc17 v en 2v/div v out 1v/div v pwrgd 2v/div 400s/div 0v 0v 0v
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v in = 5v, output voltage = 1.8v, i load = 4a, and t a = +25c, circuit of figure 1, unless otherwise noted.) pin description bump name function a1, a2 gnd analog/power ground. connect gnd to the pcb ground plane at one point near the input bypass capacitor return terminal as close as possible to the device. a3, a4 in power-supply input. input supply range is from 2.9v to 5.5v. bypass in to gnd with a 22f ceramic capacitor in parallel to a 0.1f ceramic capacitor as close as possible to the device. b1, b2, b3 lx inductor connection. all lx bumps are internally connected together. connect all lx bumps to the switched side of the inductor. lx is high impedance when the device is in shutdown mode. b4 v dd 3.3v ldo output. v dd powers the internal analog core. connect a low-esr, ceramic capacitor with a minimum value of 2.2f from v dd to gnd. c1 bst high-side mosfet driver supply. connect bst to lx with a 0.1f capacitor. c2, c3 i.c. internally connected. leave unconnected or connect to ground. c4 en enable input. connect en to gnd to disable the device. connect en to in to enable the device. d1 pwrgd power-good output. pwrgd is an open-drain output that goes high impedance when v fb exceeds 92.5% of v refin/ss and v refin/ss is above 0.54v. pwrgd is internally pulled low when v fb falls below 90% of v refin/ss or v refin/ss is below 0.54v. pwrgd is internally pulled low when the device is in shutdown mode, v dd is below the internal uvlo threshold, or the device is in thermal shutdown. d2 fb feedback input. connect fb to the center tap of an external resistor-divider from the output to gnd to set the output voltage from 0.6v to 90% of v in . d3 comp voltage-error amplifier output. connect the necessary compensation network from comp to fb and the converter output (see the compensation design section). comp is internally pulled to gnd when the device is in shutdown mode. d4 refin/ss external reference input/soft-start timing capacitor connection. connect refin/ss to a system voltage to force fb to regulate to refin/ss voltage. refin/ss is internally pulled to gnd when the device is in shutdown and thermal shutdown mode. if no external reference is applied, the internal 0.6v reference is automatically selected. refin/ss is also used to perform soft-start. connect a minimum of 1nf capacitor from refin/ss to gnd to set the startup time (see the soft-start and reference input (refin/ss) section). case temperature vs. ambient temperature max15050 toc18 ambient temperature (c) case temperature (c) 60 35 10 -15 -20 0 20 40 60 80 100 -40 -40 85 i load = 4a transition from skip mode to forced pwm max15050 toc19 i out 2a/div v lx 5v/div v out 500mv/div 10ms/div transition from forced pwm to skip mode max15050 toc20 i out 2a/div v lx 5v/div v out 500mv/div 10ms/div
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package 8 _______________________________________________________________________________________ block diagram control logic in lx gnd ilim threshold in bst thermal shutdown soft-start voltage reference bias generator oscillator 1v p-p v ramp shutdown control uvlo circuitry v dd 3.3v (ldo) shdn fb 0.9 x v refin/ss fb comp gnd pwrgd error amplifier pwm comparator current-limit comparator ilim threshold bst switch shdn lx comp clamps en refin/ss current-limit comparator max15050 max15051
max15050/max15051 c9 0.1 f optional c1 22 f output 1.8v/4a input 2.9v to 5.5v c3 0.1 f bst lx in v dd fb comp c12 56pf c10 1000pf c11 1500pf r4 5.62k ? r5 20k ? pwrgd l1 0.82 h c8 0.033 f c2 47 f r6 71.5 ? c4 0.01 f c5 2.2 f refin/ss gnd v dd max15050 max15051 u1 in en on off bst lx lx r10 2.2 ? c15 1000pf gnd r3 8.06k ? 1% r7 4.02k ? 1% high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package _______________________________________________________________________________________ 9 figure 1. all-ceramic capacitor design with v out = 1.8v detailed description the max15050/max15051 high-efficiency, voltage- mode switching regulators can deliver up to 4a of out- put current. the max15050/max15051 provide output voltages from 0.6v to (0.9 x v in ) from 2.9v to 5.5v input supplies, making them ideal for on-board point-of-load applications. the output-voltage accuracy is better than 1% over load, line, and temperature. the max15050/max15051 feature a 1mhz fixed switch- ing frequency, allowing the user to achieve all-ceramic capacitor designs and fast transient responses. the high operating frequency minimizes the size of external com- ponents. the max15050/max15051 are available in a 2mm x 2mm, 16-bump (4 x 4 array), 0.5mm pitch wlp package. the refin/ss function makes the max15050/max15051 ideal solutions for ddr and track- ing power supplies. using internal low-r ds(on) (24m ? and 18m ? ) n-channel mosfets for the high- and low- side switches, respectively, maintains high efficiency at both heavy-load and high-switching frequencies. the max15050/max15051 employ voltage-mode con- trol architecture with a high-bandwidth (> 26mhz) error amplifier. the op-amp voltage-error amplifier works with type iii compensation to fully utilize the bandwidth of the high-frequency switching to obtain fast transient response. adjustable soft-start time provides flexibilities to minimize input startup inrush current. an open-drain, power-good (pwrgd) output goes high impedance when v fb exceeds 92.5% of v refin/ss and v refin/ss is above 0.54v. pwrgd goes low when v fb falls below 90% of v refin/ss or v refin/ss is below 0.54v. controller function the controller logic block is the central processor that determines the duty cycle of the high-side mosfet under different line, load, and temperature conditions. under normal operation, where the current-limit and temperature protection are not triggered, the controller logic block takes the output from the pwm comparator and generates the driver signals for both high-side and low-side mosfets. the control logic block controls the break-before-make logic and the timing for charging the bootstrap capacitors. the error signal from the volt- age-error amplifier is compared with the ramp signal generated by the oscillator at the pwm comparator to produce the required pwm signal. the high-side switch turns on at the beginning of the oscillator cycle and typical application circuit
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package 10 ______________________________________________________________________________________ turns off when the ramp voltage exceeds the v comp signal or the current-limit threshold is exceeded. the low-side switch then turns on for the remainder of the oscillator cycle. skip mode (max15050) the max15050 features a skip function. in skip mode, the max15050 switches only as necessary to maintain the output at light loads (not capable of sinking current from the output). this maximizes light-load efficiency and reduces the input quiescent current. in skip mode, the low-side switch is turned off when the inductor current decreases to 0.2a (typ) to ensure no reverse current flowing from the output capacitor. the high-side switch minimum on-time is controlled to guarantee that 0.9a current is reached to avoid high frequency bursts at no-load conditions, which prevents a rapid increase of the supply current caused by addi- tional switching losses. under heavy load, the device operates as a pwm converter. current limit the internal, high-side mosfet has a typical 8a peak current-limit threshold. when current flowing out of lx exceeds this limit, the high-side mosfet turns off and the low-side mosfet turns on. the low-side mosfet remains on until the inductor current falls below the low- side current limit. this lowers the duty cycle and caus- es the output voltage to droop until the current limit is no longer exceeded. the max15050/max15051 use a hiccup mode to prevent overheating during short-cir- cuit output conditions. during current limit, if v fb drops below 70% of v refin/ss and stays below this level for typically 36s or more, the device enters hiccup mode. the high-side mosfet and the low-side mosfet turn off and both comp and refin/ss are internally pulled low. the device remains in this state for 896 clock cycles and then attempts to restart for 112 clock cycles. if the fault- causing current limit has cleared, the device resumes normal operation. otherwise, the device reenters hic- cup mode. soft-start and reference input (refin/ss) the max15050/max15051 utilize an adjustable soft- start function to limit inrush current during startup. an 8a (typ) current source charges an external capacitor connected to refin/ss. the soft-start time is adjusted by the value of the external capacitor from refin/ss to gnd. the required capacitance value is determined as: where t ss is the required soft-start time in seconds. connect a minimum 1nf capacitor between refin/ss and gnd. refin/ss is also an external reference input (refin/ss). the device regulates fb to the voltage applied to refin/ss. the internal soft-start is not avail- able when using an external reference. figure 2 shows a method of soft-start when using an external refer- ence. if an external reference is not applied, the device uses the internal 0.6v reference. undervoltage lockout (uvlo) the uvlo circuitry inhibits switching when v dd is below 2.55v (typ). once v dd rises above 2.6v (typ), uvlo clears and the soft-start function activates. a 50mv hysteresis is built-in for glitch immunity. bst the gate-drive voltage for the high-side, n-channel switch is generated by a flying-capacitor boost circuit. the capacitor between bst and lx is charged from the v in supply while the low-side mosfet is on. when the low-side mosfet is switched off, the voltage of the capacitor is stacked above lx to provide the necessary turn-on voltage for the high-side internal mosfet. power-good output (pwrgd) pwrgd is an open-drain output that goes high impedance when v fb is above 92.5% x v refin/ss and v refin/ss is above 0.54v. pwrgd pulls low when v fb is below 90% of v refin/ss for at least 48 clock cycles or v refin/ss is below 0.54v. pwrgd is low during shutdown. c at v ss = 8 06 . c r2 r1 refin/ss max15050 max15051 figure 2. typical soft-start implementation with external reference
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package ______________________________________________________________________________________ 11 setting the output voltage the max15050/max15051 output voltage is adjustable from 0.6v to 90% of v in by connecting fb to the center tap of a resistor-divider between the output and gnd (figure 3). to determine the values of the resistor- divider, first select the value of r3 between 2k ? and 10k ? . then use the following equation to calculate r4: r4 = (v fb x r3)/(v out - v fb ) where v fb is equal to the reference voltage at refin/ss and v out is the output voltage. for v out = v fb , remove r4. if no external reference is applied at refin/ss, the internal reference is automatically select- ed and v fb becomes 0.6v. shutdown mode drive en to gnd to shut down the device and reduce quiescent current to less than 10a. during shutdown, lx is high impedance. drive en high to enable the max15050/max15051. thermal protection thermal-overload protection limits total power dissipa- tion in the device. when the junction temperature exceeds t j = +165c, a thermal sensor forces the device into shutdown, allowing the die to cool. the ther- mal sensor turns the device on again after the junction temperature cools by 20c, causing a pulsed output during continuous overload conditions. the soft-start sequence begins after recovery from a thermal-shut- down condition. applications information in and v dd decoupling to decrease the noise effects due to the high switching frequency and maximize the output accuracy of the max15050/max15051, decouple v in with a 22f capacitor in parallel with a 0.1f capacitor from v in to gnd. also decouple v dd with a 2.2f capacitor from v dd to gnd. place these capacitors as close as possible to the device. inductor selection choose an inductor with the following equation: where lir is the ratio of the inductor ripple current to full load current at the minimum duty cycle and f s is the switching frequency (1mhz). choose lir between 20% to 40% for best performance and stability. use an inductor with the lowest possible dc resistance that fits in the allotted dimensions. powdered iron or fer- rite core types are often the best choice for perfor- mance. with any core material, the core must be large enough not to saturate at the current limit of the max15050/max15051. output-capacitor selection the key selection parameters for the output capacitor are capacitance, esr, esl, and voltage-rating require- ments. these affect the overall stability, output ripple voltage, and transient response of the dc-dc convert- er. the output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitors esr, and the voltage drop due to the capacitors esl. estimate the output-voltage ripple due to the output capacitance, esr, and esl as fol- lows: where the output ripple due to output capacitance, esr, and esl is: whichever is higher. v i t x esl ripple esl pp off () = ? and v i t ripple esl pp on () = ? x x esl or vix ripple esr p p () = ? e esr v i xc xf ripple c pp out s () = ? 8 vv vv ripple ripple c ripple esr ripple esl =+ + () () () l vvv f v lir i out in out s in out max = ? () () lx fb r3 r4 max15050 max15051 figure 3. setting the output voltage with a resistor voltage- divider
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package the peak-to-peak inductor current (i p-p ) is: use these equations for initial output-capacitor selec- tion. determine final values by testing a prototype or an evaluation circuit. a smaller ripple current results in less output-voltage ripple. since the inductor ripple current is a factor of the inductor value, the output-voltage rip- ple decreases with larger inductance. use ceramic capacitors for low esr and low esl at the switching frequency of the converter. the ripple voltage due to esl is negligible when using ceramic capacitors. load-transient response depends on the selected out- put capacitance. during a load transient, the output instantly changes by esr x ? i load . before the con- troller can respond, the output deviates further, depending on the inductor and output capacitor val- ues. after a short time, the controller responds by regu- lating the output voltage back to its predetermined value. the controller response time depends on the closed-loop bandwidth. a higher bandwidth yields a faster response time, preventing the output from deviat- ing further from its regulating value. see the compen- sation design section for more details. the minimum recommended output capacitance for the max15051 and max15051 is 47f and 22f, respectively. input-capacitor selection when transitioning from skip mode to pwm mode (max15050) with a large current load step, additional out- put capacitance can be used to help minimize the load- transient response. the input capacitor reduces the current peaks drawn from the input power supply and reduces switching noise in the device. the total input capacitance must be equal to or greater than the value given by the following equation to keep the input ripple voltage within the specification and minimize the high-fre- quency ripple current being fed back to the input source: where v in-ripple is the maximum-allowed input ripple voltage across the input capacitors and is recommend- ed to be less than 2% of the minimum input voltage, d is the duty cycle (v out /v in ), t s is the switching period (1/f s ) = 1s, and i out is the output load. the impedance of the input capacitor at the switching fre- quency should be less than that of the input source so high-frequency switching currents do not pass through the input source, but are instead shunted through the input capacitor. the input capacitor must meet the ripple current requirement imposed by the switching currents. the rms input ripple current is given by: where i ripple is the input rms ripple current. compensation design the power transfer function consists of one double pole and one zero. the double pole is introduced by the inductor, l, and the output capacitor, c o . the esr of the output capacitor determines the zero. the double pole and zero frequencies are given as follows: where r l is equal to the sum of the output inductors dc resistance (dcr) and the internal switch resistance, r ds(on) . a typical value for r ds(on) is 25m ? . r o is the output load resistance, which is equal to the rated output voltage divided by the rated output current. esr is the total equivalent series resistance of the output capacitor. if there is more than one output capacitor of the same type in parallel, the value of the esr in the above equation is equal to that of the esr of a single output capacitor divid- ed by the total number of output capacitors. the max15050/max15051 high switching frequency allows the use of ceramic output capacitors. since the esr of ceramic capacitors is typically very low, the frequency of the associated transfer function zero is higher than the unity-gain crossover frequency, f c , and the zero cannot be used to compensate for the double pole created by the output inductor and capacitor. the double pole produces a gain drop of 40db/decade and a phase shift of 180. the compensation network must compensate for this gain drop and phase shift to achieve a stable high-bandwidth closed- loop system. therefore, use type iii compensation as shown in figure 4 and figure 5. type iii compensation possesses three poles and two zeros with the first pole, f p1_ea , located at zero frequency (dc). locations of other poles and zeros of the type iii compensation are given by: f xr xc zea 2 1 233 _ = f xr xc zea 1 1 211 _ = f x esr x c z esr o _ = 1 2 ff xlxc x r esr rr plc p lc o o ol 12 1 2 __ == + + ? ? ? ? ? ? ii vvv v ripple load out in out in = ? () c dxt xi v in min sout in ripple _ = ? i vv fl x v v pp in out s out in ? = ? 12 ______________________________________________________________________________________
max15050/max15051 the above equations are based on the assumptions that c1 >> c2, and r3 >> r2, which are true in most appli- cations. placements of these poles and zeros are deter- mined by the frequencies of the double pole and esr zero of the power transfer function. it is also a function of the desired closed-loop bandwidth. the following section outlines the step-by-step design procedure to calculate the required compensation components for the max15050/max15051. the output voltage is determined by: where v fb is the feedback voltage equal to v refin/ss or 0.6v depending whether or not an external reference voltage is applied to refin/ss. for v out = v fb , r4 is not needed. the zero-cross frequency of the closed-loop, f c , should be between 10% and 20% of the switching frequency, f s (1mhz). a higher zero-cross frequency results in faster transient response. once f c is chosen, c1 is cal- culated from the following equation: where v p-p = 1v p-p (typ). due to the underdamped nature of the output lc double pole, set the two zero frequencies of the type iii compen- sation less than the lc double-pole frequency to provide adequate phase boost. set the two zero frequencies to 80% of the lc double-pole frequency. hence: setting the second compensation pole, f p2_ea , at f z_esr yields: set the third compensation pole at 1/2 of the switching frequency (500khz) to gain phase margin. calculate c2 as follows: the above equations provide accurate compensation when the zero-cross frequency is significantly higher than the double-pole frequency. when the zero-cross frequency is near the double-pole frequency, the actual zero-cross frequency is higher than the calculated fre- quency. in this case, lowering the value of r1 reduces the zero-cross frequency. also, set the third pole of the type iii compensation close to the switching frequency (1mhz) if the zero-cross frequency is above 200khz to boost the phase margin. the recommended range for r3 is 2k ? to 10k ? . note that the loop compensation remains unchanged if only r4s resistance is altered to set different outputs. c xr x f s 2 1 1 = r c x esr c o 2 3 = c xr x l x c x r esr rr oo lo 3 1 08 3 = + + . () r xc x l x c x r esr rr oo lo 1 1 08 1 = + + . () c v v xxrx r r f in pp l o c 1 1 5625 231 = ? ? ? ? ? ? + ? . () r vr vv fb out fb 4 3 = ? () f x pea 3 1 2 _ = r rxc 12 f xr xc pea 1 223 2_ = high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package ______________________________________________________________________________________ 13 l c out v out r3 r4 r1 comp fb lx c1 c3 r2 c2 max15050 max15051 figure 4. type iii compensation network double pole gain (db) freuency (hz) second pole first and second zeros power-stage transfer function compensation transfer function open-loop gain third pole figure 5. type iii compensation illustration
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package 14 ______________________________________________________________________________________ soft-starting into a prebiased output the max15050/max15051 can soft-start into a prebi- ased output without discharging the output capacitor. in safe prebiased startup, both low-side and high-side switches remain off to avoid discharging the prebiased output. pwm operation starts when the voltage on refin/ss crosses the voltage on fb. the pwm activity starts with the low-side switch turning on first to build the bootstrap capacitor charge. power-good (pwrgd) asserts 48 clock cycles after fb crosses 92.5% of the final regulation set point. after 4096 clock cycles, the max15050 switches from prebiased safe-startup mode to either a skip mode or a forced pwm mode depend- ing on whether the inductor current reaches zero. the max15051 switches from the prebiased safe-startup mode to forced pwm mode regardless of inductor cur- rent level. the max15051 also can start into a prebiased voltage higher than the nominal set point without abruptly dis- charging the output. this is achieved by using the sink current control of the low-side mosfet, which has four internally set sinking current-limit thresholds. an internal 4-bit dac steps through these thresholds, starting from the lowest current limit to the highest, in 128 clock cycles on every power-up. pcb layout considerations and thermal performance careful pcb layout is critical to achieve clean and sta- ble operation. it is highly recommended to duplicate the max15050/max15051 evaluation kit layout for opti- mum performance. if deviation is necessary, follow these guidelines for good pcb layout: 1) place capacitors on in, v dd , and refin/ss as close as possible to the device and the corre- sponding bump using direct traces. 2) keep the high-current paths as short and wide as possible. keep the path of switching current short and minimize the loop area formed by lx, the out- put capacitors, and the input capacitors. 3) connect in, lx, and gnd separately to a large copper area to help cool the device to further improve efficiency and long-term reliability. 4) ensure all feedback connections are short. place the feedback resistors and compensation compo- nents as close to the device as possible. 5) route high-speed switching nodes, such as lx and bst, away from sensitive analog areas (fb, comp). chip information process: bicmos wlp gnd in in gnd a1 a2 a3 a4 b1 b2 b3 b4 c1 c2 c3 c4 d1 d2 d3 d4 lx lx v dd lx i.c. i.c. en bst pwrgd fb comp refin/ss top view (bumps on bottom) max15050/max15051 pin configuration package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 16 wlp w162c2+1 21-0200
max15050/max15051 high-efficiency, 4a, 1mhz, step-down regulators with integrated switches in 2mm x 2mm package maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 8/09 initial release. 1 10/09 remove future product asterisk for max15051, update electrical characteristics table and typical operating characteristics . 1, 2, 4, 5, 6, 12, 14 2 3/10 revised absolute maximum ratings and electrical characteristics table global and note. 2, 3, 4

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